CMOS or CCD image sensors are of interest in a wide variety of sensing and imaging applications in a wide range of fields including consumer, commercial, industrial, and space electronics. Imagers based on charge coupled devices (CCDs) are currently the most widely utilized. CCDs are employed either in front or back illuminated configurations. Front illuminated CCD imagers are more cost effective to manufacture than back illuminated CCD imagers such that front illuminated devices dominate the consumer imaging market. Front-illuminated imagers, however, have significant performance limitations such as low fill factor/low sensitivity. The problem of low fill factor/low sensitivity is typically due to shadowing caused by the presence of opaque metal bus lines, and absorption by an array circuitry structure formed on the front surface in the pixel region of a front-illuminated imager. Thus, the active region of a pixel is typically relatively small (low fill factor) in large format (high-resolution) front-illuminated imagers.
Back-illuminated semiconductor (CCD and CMOS) imaging devices are advantageous over front-illuminated imagers for high fill factor, better overall efficiency of charge carrier generation and collection, and are suitable for small pixel arrays. Fabrication of thinned back illuminated imagers has several challenges. One challenge is the loss of charge carriers near the back surface due to inherent dangling bonds present at the silicon back surface, which reduces Quantum Efficiency (QE) if the backside of the thinned imager is not pinned. Eliminating this problem requires additional treatment at the backside of the device, which adds to the complexity of the fabrication process.
A second challenge is absorption of charge carriers within the epitaxial layer, which prevents charge carriers from reaching processing components on the front side, which reduces sensitivity and efficiency of the device. In back illuminated imagers, photon radiation that enters the backside of the imagers generates charge carriers in the silicon epitaxial layer. The location of the charge generation in the epitaxial layer depends on the absorption length of the incident photon, which in turn depends on its wavelength. Photons with longer wavelengths, such as red, penetrate deeper into the epitaxial layer as compared to shorter wavelengths, such as blue. To generate maximum charge carriers from all the incident photons of different wavelengths requires an appropriate thickness for the epitaxial layer. Further, charge carriers generated near the back side of the imager should be driven to the front side as quickly as possible in order to avoid horizontal drift of carriers into adjacent pixels, which may smear an image.
Additional challenges include excessive thinning of wafers, which poses yield issues such as stress in the thinned wafer, and uniformity of thickness, etc. Fabrication cost of back illuminated imagers can be higher than for front illuminated imagers due to thinning and backside treatment.
To overcome these problems, techniques employing ultra thin silicon-on-insulator (SOI) wafers for the fabrication of back illuminated CCD/CMOS imagers have been developed, an example of which is described in U.S. Pat. No. 7,238,583 (hereinafter “the '583 Patent”), which is incorporated by reference herein in its entirety. In the '583 Patent, a thin semiconductor seed layer is supported by an ultra-thin substrate and an insulator layer made of an electrically insulating material such as silicon dioxide. An epitaxial layer may be grown substantially overlying the seed layer to an appropriate thickness to accommodate devices that are to operate at wavelengths from less than 100 nanometers (deep ultraviolet) to more than 3000 nanometers (far infrared). In order to drive charge carriers to the front side without recombination near the back side, and to prevent horizontal drift, a large electric field needs to be generated within the device. This is accomplished by doping the insulation and seed layers at an initial concentration, growing the epitaxial layer on the seed layer, and then causing the dopant to diffuse into the epitaxial layer such that the final net doping profile has its highest concentration in the insulator layer, with the net doping profile decreasing monotonically within the insulator layer and epitaxial layer.
This technique solves the aforementioned problems. However, as technology advances in the fabrication of CMOS devices, the current CMOS imaging market demands high pixel density, and hence small pixel size for imagers. The scaling of pixel size also results in a lower bias supply. This limits the drift field that can be produced in a small pixel back illuminated imager array. Charge carriers that are generated near the backside due to short wavelength photons will tend to diffuse to the adjacent pixel, if there is not enough drift field. This phenomenon, which is referred as crosstalk, can be worse for a small pixel back illuminated array. Furthermore, photons that have a non-perpendicular incident angle relative to the back-side surface may generate carriers in adjacent pixels, which is a form of optical crosstalk.
Accordingly, what would be desirable, but has not yet been provided, are a method and resulting device that reduces crosstalk in back illuminated imagers. Such a method and device would employ the doping profile technique disclosed in the '583 Patent where SOI wafers are used as a starting material.